1. Field
The present disclosure relates to fault-tolerance techniques for semiconductor memory devices. More specifically, the present disclosure relates to a memory device which uses a bit-replacement technique to remap faulty memory cells to replacement cells.
2. Background
As feature sizes on DRAM devices continue to decrease, it is becoming progressively harder to maintain existing levels of memory-cell capacitance. Consequently, as feature sizes continue to decrease, memory-cell capacitance also decreases, which causes a corresponding decrease in data retention times. This means that a larger percentage of memory cells will be unable to meet minimum data retention time requirements, which can adversely affect manufacturing yield for DRAM devices.